In modern integrated circuit (IC) fabrication, layers of material are applied to embedded structures previously formed on semiconductor wafers. Chemical mechanical planarization (CMP) is an abrasive process used to remove these layers and polish the surface of a wafer flat to achieve the desired structure. CMP may be performed on both oxides and metals and generally involves the use of chemical slurries applied via a polishing pad that is moved relative to the wafer (e.g., the pad may rotate circularly relative to the wafer). The resulting smooth, flat surface is necessary to maintain the photolithographic depth of focus for subsequent steps and to ensure that the metal interconnects are not deformed over contour steps.
The planarization/polishing performance of a pad/slurry combination is impacted by, among other things, the mechanical properties and slurry distribution ability of the polishing pad. Typically, hard (i.e., stiff) pads provide good planarization, but are associated with poor with-in wafer non-uniformity (WIWNU) film removal. Soft (i.e., flexible) pads, on the other hand, provide polishing with good WIWNU, but poor planarization. In conventional CMP systems, therefore, harder pads are often placed on top of softer pads to improve WIWNU. Nevertheless, this approach tends to degrade planarization performance when compared to use of a hard pad alone.
It is therefore the case that designing CMP polishing pads requires a trade-off between WIWNU and planarization characteristics of the pads. This trade-off has led to the development of polishing pads acceptable for processing dielectric layers (such as silicon dioxide) and metals such as tungsten (which is used for via interconnects in subtractive processing schemes). In copper processing, however, WIWNU directly impacts over-polishing (i.e., the time between complete removal of copper on any one area versus complete removal from across an entire wafer surface) and, hence, metal loss and, similarly, planarization as expressed by metal loss. This leads to variability in the metal remaining in the interconnect structures and impacts performance of the integrated circuit. It is therefore necessary that both planarity and WIWNU characteristics of a pad be optimized for best copper process performance.
Some of the above-described concepts can be illustrated graphically. FIG. 1A illustrates the surface of a post-CMP wafer 100 with copper interconnects 104 defined in a low-K dielectric layer 102. Stress induced cracking damage 106 is seen on the surface of the dielectric layer 102, as a result of using a conventional polishing pad.
In addition to monitoring pressures, the ability to monitor process conditions while a wafer is being polished is important as it can provide information on the wafer surface, which, in turn, may be utilized to change the process conditions or stop processing all together. In the case of copper CMP for example, the actual copper thickness may be monitored to change the process conditions when a wafer has only a predetermined thickness of copper remaining or to change polishing slurry when all copper has been cleared. More than one type of feedback maybe required to understand the processing of the wafer. For example, in the case of copper processing, temperature rises during polishing of a copper film. The slope of this rise as well as the magnitude of the rise gives information on not only removal rate, but may also be able to provide insight into the behavior of the slurry.
FIG. 1B illustrates the surface of a copper wafer 108 after electroplated copper 110 has been deposited. Conformal filling of the copper 110 over large features 112 is evident, while overlay of smaller features 114 shows no such topography. FIG. 1C illustrates the surface of the wafer 108 post-CMP. Dishing and erosion of the features (108, and 110 respectively) is now evident. Dishing and erosion increase with over-polishing, hence there is a need to minimize over-polishing of copper wafers.